1. Field of the Invention
The present invention relates to a semiconductor device having a fuse barrier pattern and a fabrication method thereof. More particularly, the present invention relates to a semiconductor device having a fuse barrier pattern that is located between each fuse in a fuse region of the semiconductor device and a fabrication method thereof.
2. Description of the Related Art
Semiconductor memory devices are commonly tested using an electrical tester in a wafer-level state before they are assembled into a package-level state. As the result of the testing, they can be sorted into properly functioning chips and malfunctioning chips.
If the malfunctioning chips have just a few failing cells, the cells that are identified as failing can be repaired by exchanging the failing cells with redundant cells. Such a repair process commonly includes a fuse blowing step that employs a laser beam in order to reassign the failing cells with the new addresses of the redundant cells for data reading and writing.
In the case of conventional semiconductor memory devices, the fuses are generally formed in the same fabrication step with the formation of bit-lines or word-lines. Therefore, the fuses are commonly formed at the same elevation as those of the bit-lines or word-lines. A dielectric layer is deposited on the resulting fuse.
FIG. 1 is a cross-sectional view illustrating a fuse region of a conventional semiconductor memory device.
Referring to FIG. 1, a dielectric layer 12 is deposited on a semiconductor substrate 10. A plurality of fuses 15 are formed on the dielectric layer. An inter-metallic dielectric layer 20 is formed on the plurality of fuses 15. In order to blow, open, or cut, the plurality of fuses, a fuse window 25 is formed in the inter-metallic dielectric layer by partially etching the inter-metallic dielectric layer 20. Therefore, a portion of the inter-metallic dielectric layer 20 remains on the plurality of fuses 15.
Repair processes can be performed by blowing one or more of the fuses with a laser beam. However, if the inter-metallic dielectric layer 20 remaining on the bottom portion of the fuse window 25 on the plurality of fuses 15 is too thick, it can be difficult to completely blow, or open, the fuse to be opened. Thus, residue of the fuse can remain in the inter-metallic dielectric layer 20, especially at the bottom sidewalls of the fuse, as shown in region S of FIG. 1.
If the energy of the laser beam is increased to a higher level in order to ensure complete opening of the fuse, an adjacent fuse that is located beside the blown fuse can be damaged by the high energy laser beam. With the continuous increase of semiconductor device integration density, the distance between each fuse continues to become smaller. As a result, it becomes more difficult to blow a fuse precisely and completely.
In order to solve this problem mentioned above in contemporary systems, the thickness of the inter-metallic dielectric layer 20 remaining on the plurality of fuses at the bottom of the fuse window 25 is made to be thinner, even if the inter-metallic dielectric layer 20 is etched in the fuse window region 25 to a degree such that the top surfaces of the plurality of fuses are exposed. In this case, even though it is possible to blow the fuse completely, the broken pieces of the blown fuse can adhere to the adjacent, non-selected, fuses which are not to be opened, thereby electrically connecting, or shorting, adjacent fuses. This, in turn, can cause the semiconductor memory device to malfunction.